1. Field of the Invention
The present invention relates to an information processing apparatus adopting an out-of-order process system. In particular, the present invention relates to an instruction processing device for controlling a branch instruction accompanied by a mode change by way of hardware in an information processing apparatus with a plurality of ports for an instruction fetch, and a method thereof.
2. Description of the Related Art
In an information processing apparatus adopting an out-of-order processing system, subsequent instruction strings are sequentially inputted to a plurality of pipelines before one instruction execution is completed, and performance is improved by executing the instructions using those pipelines.
However, if the execution result of a present instruction affects the execution of a subsequent instruction, the subsequent instruction cannot be executed before the execution of the present instruction is completed. If an instruction process which affects the execution of a subsequent instruction is delayed, a subsequent instruction cannot be executed during the delay and continues to wait for the completion of the execution of the present instruction. Accordingly, disorder occurs in a pipeline and the performance of an instruction process is degraded.
A branch instruction is a typical example of such an instruction. In a branch instruction, since whether the branch occurs is unknown until the execution is completed and the target address of the branch destination is also unknown, a subsequent instruction is held and the pipeline is disturbed.
Under these circumstances, the high-speed execution of a branch instruction is promoted by using a branch history (branch prediction table). If a branch prediction using a branch history is made when a branch instruction is executed, a subsequent instruction and a branch destination instruction can be processed before it is determined whether the branch occurs.
According to this process system, if a branch instruction is executed, and as a result, it is found that the branch occurs, the instruction address of a branch destination and the instruction address of the branch instruction itself are paired and registered in a branch history in advance. When the instruction is extracted from a main storage device, the branch history is retrieved prior to the execution of the instruction.
In this way, pairs of the instruction address of a branch instruction that is previously branched and the instruction address of a branch destination are registered in a branch history. A branch instruction which is not registered in a branch history and has been branched must be newly registered in the branch history. If the target address of the branch destination of a branch instruction is changed for some reason, the target address of the branch destination obtained by retrieving it from the branch history becomes invalid.
Out of the entries of a branch history, entries corresponding to the following cases are considered to have a high possibility of failing in a branch prediction and are removed from the branch history:    (1) a prediction that a branch is taken fails twice in succession    (2) a prediction that a branch is taken fails and the target address of a branch destination is also incorrect    (3) an instruction is registered by mistake although the instruction is not actually a branch instruction
If a prediction that a branch is taken fails or the target address of a branch destination is incorrect, such information must be stored for each target.
However, the conventional instruction process described above has the following problem.
According to the conventional instruction processing device, since an address mode indicating the bit size of an address space is determined by software, the address mode is sometimes changed while an instruction is executed. However, when the branch prediction of a branch instruction accompanied by an address mode change is made, only the instruction address of a branch destination can be predicted since a mechanism for predicting the address mode of a branch destination is not provided. Therefore, the pre-fetch of a branch destination instruction string cannot be performed based on the changed address mode, and thereby a correct instruction process cannot be executed.
When the instruction address of a branch destination is calculated and obtained using an address generator, the address mode of the branch destination can not also be obtained. When the pre-fetch of an instruction is performed at a specific port in an instruction process device provided with a plurality of instruction fetch ports and then the fetch is attempted to be restored to a sequential instruction fetch at another port, a correct instruction process cannot also be executed if the address modes of the respective ports are different.
In this way and according to the conventional instruction process device, if an address mode is changed, a correct instruction process is sometimes not executed. Accordingly, control using a micro-program becomes necessary and thereby the number of clocks needed for the control increases, which is a problem.